1. Field of the Invention
This invention relates to the method of manufacturing semiconductor integrated circuits and more particularly to an improved method for making contact holes to semiconductor integrated circuit devices which contain a plurality of field effect transistors.
2. Description of the Prior Art
Semiconductor devices such as, for example, conventional silicon gate MOS transistor as shown in FIG. 1 are manufactured by forming on the surface of P-type Silicon substrate 1 a relatively thick field oxide layer 2. A predetermined part of this field oxide layer 2 is removed and in this removed portion field effect transistors are formed. In this example, by using gate 4 and the field oxide layer 2 as a mask, impurities such as phosphorus are diffused to the P-type silicon substrate, thereby forming n+ regions 5 and 6 which serve as source and drain, respectively. Gate 4 is formed of polysilicon material, and when forming polysilicon gate electrode 4 also polysilicon metallization 7 is formed. After making the necessary field effect transistors on the total surface of the device, a CVD oxide layer 8 is deposited. Thereafter, a contact hole is formed. The area of this contact hole W is normally w.times.w (w=5 to 6 .mu.m). By using recent techniques w can be reduced to 4 .mu.m, but to be practical from a reliability point of view, it is important that tolerances be provided. Firstly, because the field oxide 2 serves as a mask for subsequent n+ diffusion, to avoid the electrical short circuit of the electrode 9 or 10 and the p-type substrate 1 tolerance s as denoted in FIG. 1, which is normally chosen on the order of 2 .mu.m, is provided. This value 2 .mu.m is defined in consideration of the side etching and the precision of mask alignment. Then, in relation to the polysilicon gate electrode 4, the tolerance r is needed to avoid the electrical short circuit of aluminum metallization 9 and polysilicon gate electrode 4. Tolerance r is practically chosen on the order of 3 to 4 .mu.m. Tolerance should be also considered as for the polysilicon metallization 7. That is, when the contact holes or the opening is made extending the edge of the polysilicon metallization 7 and the surface of the field oxide 2 is revealed. Then the underpart of the edge of the polysilicon metallization 7 is etched resulting in the formation of so-called overhang of the metallization 7. This overhang will result in the cutting of the metallization. To avoid this, it is also needed to provide a tolerance t on the order of 2 .mu.m.
The above mentioned tolerances are primary factors limiting reductions in chip size of large-scaled semiconductor integrated circuits.